1. Field of the Invention
The present invention relates to an improved silicon semiconductor wafer and to a process for simultaneous double-side polishing of a multiplicity of silicon semiconductor wafers. Silicon semiconductor wafers are used as base material for the fabrication of electronic components.
2. The Prior Art
Even if in some cases compound semiconductors, such as gallium arsenide, are used as the basis for special applications in the electronic components sector, the majority of wafers for use in the semiconductor industry employ silicon as the semiconducting substrate material. Modern components with integrated circuits, for example processors or memory components, are nowadays generated on silicon wafers with diameters of up to 300 mm, in some cases in 400 to 500 process steps. The individual results of these steps are multiplied over a fabrication sequence of this type and have to be monitored and optimized as accurately as possible with a view to achieving an economically viable overall yield. In addition to the process stability of these individual processes, the quality of the silicon wafers used also plays a critical role which is reflected in a wide range of specification parameters which predominantly relate to the wafer as a whole or to the front surface, to which components are intended to be applied.
By way of example, the silicon wafer must have a high flatness in all subregions, in order to take into account the requirements of exposure processes for the application of photomasks. These photomasks protect specific regions from subsequent operations, such as ion implantation, deposition steps or etching processes and thus allow component structures to be produced. The local flatness can be described by the SFQR value, whereby the silicon wafer is covered by an imaginary component grid, for the partial areas of which it is possible to determine the SFQR values. The highest value on a silicon wafer, the SFQRmax, is often specified. Excessively high values lead to focussing problems with the stepper used to apply the photomasks and therefore to loss of the component in question. In this context, it should be borne in mind that in this process the silicon wafer is generally held by applying a vacuum to a nondeformable support (chuck), for example made from ceramic which has been ground to a high flatness. The local flatnesses of wafer and support are cumulative via the sum of the square roots; this intensifies the demands imposed on the silicon wafer.
Modern sequences involved in the fabrication of electronic components in some cases include planarization steps which are known to the person skilled in the art as CMP (chemical mechanical planarization) polishing and level out SiO2 layers which have been deposited, for example, using the CVD (chemical vapor decomposition) process, with a high level of precision when relatively hard polishing cloths are used. The coated silicon wafers are (generally held by adhesion, with very little or no vacuum, on a support which is covered with a soft pad, so that unevenness on the back surface can be compensated for. The homogeneity of the thickness of the SiO2 layer after the CMP polishing, which is to be regarded as a critical parameter with regard to electrical breakdowns during operation of the integrated circuit, is therefore dependent less on the local thickness distribution and more on the local height deviation of the coated front surface from an ideal plane. The indication defined in this way is a measure of the local inclination on the silicon surface. If it is too pronounced, it is impossible for the CMP polishing to remove material uniformly from the SiO2 coating, for example, in the valleys of a limited region and on the more greatly exposed peaks, which leads to the above-mentioned deviations in the layer thickness.
The local height deviation of the front surface from an ideal plane is likewise specified for surface-covering subregions of the wafer which, however, in accordance with the CMP process, are generally smaller than the component surfaces and are determined in the form of an overlapping, sliding set window. The measure used is the maximum height difference between the point located closest to the ideal plane and the point located furthest away from this plane (peak-to-valley height) in a subregion. The highest value for a specific subregion dimension n×n (in mm) for the entire wafer is often given as P/V(n×n)max. This eliminates global wafer distortion (warp), which is not critical for the CMP polishing of layers, from consideration.
A typical process sequence for the production of silicon semiconductor wafers comprises the process steps of sawing—edge rounding—lapping or grinding—wet chemical etching—polishing. While the silicon-removing steps, on account of the shaping which has been produced up to that stage, already have to perform the preliminary work in order to achieve the specified dimensional parameters and therefore have to be carefully matched to one another with regard to the conflicting areas of quality and costs. The final local flatness and the local height deviation of the front surface of the silicon wafer from an ideal plane are produced by a polishing process.
Conventional single-surface polishing processes no longer satisfy the more stringent demands imposed with regard to the abovementioned parameters. Rather, for this purpose, equipment and processes for the simultaneous double-side polishing of front surface and back surface of the silicon semiconductor wafers have been developed and are nowadays increasingly being used. The semiconductor wafers are in this case moved in carriers, which have suitably dimensioned cutouts, along a path which is predetermined by the machine and process parameters between two parallel, rotating polishing plates, which are covered with polishing cloth. This occurs in the presence of a polishing agent which contains abrasives or colloids, and as a result are polished so as to produce a high plane-parallelism. Examples of suitable polishing installations are described in DE 37 30 795 A1 and U.S. Pat. No. 6,080,048.
A polishing process which acts on both sides in order to achieve improved flatnesses is described in DE 199 05 737 C2. It is distinguished by the fact that the thickness of the fully polished semiconductor wafers is 2 to 20 μm greater than the thickness of the carriers used. DE 199 38 340 C1 has proposed a process for applying an epitaxial coating of silicon to a silicon wafer which has been polished on both sides. DE 100 12 840 C2 describes a cost-optimized process for the surface-polishing of silicon wafers which have been polished on both sides. In such cases, if a suitably dimensioned polishing installation is occupied, for example, by 15 silicon wafers with a diameter of 300 mm, a polishing pressure of 0.15 bar results in material-removal rates of 0.5 to 0.6 μm/min. Improvements to the installation and process which are described, for example, in DE 100 60 637 A1 and DE 101 54 942 A1, for the same installation configuration and the same quality demands imposed on the polished wafers, allow polishing pressures of greater than or equal to 0.20 bar, which leads to material-removal rates of greater than or equal to 0.8 μm/min.
A drawback of the double-side polishing processes according to the prior art is that silicon semiconductor wafers which, in addition to satisfying current specifications for the local flatness, also have to comply with the maximum local height deviation of the front surface from an ideal plane. In operational practice these wafers can only be manufactured at the same time as otherwise equivalent wafers which do not have to satisfy the local height deviation criterion if high process costs are accepted.